The architecture of the disclosed system is composed of: (1) a front end time encoder that converts at high speed an analog input signal into a asynchronous pulse sequence, (2) a pulse asynchronous DeMUX circuit that converts the high speed asynchronous pulse sequence into a parallel stream of pulse sequences at lower speed, (3) a parallel pulse to asynchronous digital converter, (4) an asynchronous digital to synchronous digital converter, (5) a timing reference circuit to generate absolute time references, and (6) a Digital Signal Processor.
The disclosed architecture provides an analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal. This architecture with parallelization of pulses is believed to be new to the art. Also new are the following components: (1) An IC HBT time encoder, (2) a new transistor level topology to implement a differential hysteresis quantizer, (3) the pulse deMUX circuit, (4) the parallel pulse to asynchronous digital converter, (5) the asynchronous digital to synchronous digital converter, and (6) the timing reference circuit.
Particularly important features of this architecture includes: (1) providing a pulse demultiplexing scheme that is tolerant of jitter and offsets in control signals, (2) providing a digitization scheme in which individual pulses can be digitized at a lower speed than the input signal bandwidth. The disclosed pulse demultiplexing and parallel digitization allows achieving ultra wide bandwidth.
The disclosed technology allows one to do analog to digital conversion with a higher speed-resolution performance than existing ADC architectures. This is enabled by performing three basic operations: (1) time encoding the original signal into asynchronous pulses, (2) demultiplexing and (3) digitization.
The pulse demultiplexing allows using parallel circuits that can run at a lower speed than the input signal bandwidth. The complete circuit of the invention can digitize signals at higher speed than prior art ADCs for a given resolution. Preliminary simulations of important components show that the new architecture could be used to achieve 10 GHz bandwidth and 10 bit effective resolution, which is larger speed-resolution performance specification than previously reported ADCs. See R. Walden, “Analog-to-Digital Converter Survey and Analysis,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, pp. 539-550, April 1999.
With respect to the prior art, A. Lazar and L Toth in “Perfect Recovery and Sensitivity Analysis of Time Encoded Bandlimited Signals,” IEEE Trans. on Circuits and Systems—I, vol. 51, no. 10, pp. 2060-2073, October 2004 teach a single time encoder circuit limit cycle oscillator. In this paper it is shown that an analog input signal can be converted into an asynchronous pulse sequence, and that the original input can be recovered from the pulse sequence. However, this paper is limited to study the transformation from analog domain into the pulse domain and back. No attempt is made to build an analog-to-digital converter.
E. Roza, in “Analog-to-Digital Conversion via Duty Cycle Modulation,” IEEE trans. on Circuits and Systems—II, vol. 44, no. 11, pp 907-914, November 1997 teaches a duty cycle analog to digital to digital converter architecture. However, in this architecture the conversion from pulse into digital is based simply on directly sampling the pulse signal in a synchronous way. This simple direct sampling process introduces potentially large quantization errors that are only mitigated by significantly over-sampling the synchronous clock to respect the asynchronous pulse sequence or by using poly-phase samplers. The input signal bandwidth needs to be much lower (typically by a factor as large as 1000) than the speed of synchronous sampling circuitry or the speed of basic inverter delay stages, which is limited for any given technology. The present disclosure uses a different digitization scheme without over-sampling and with pulse data parallelism and the input signal bandwidth can be much higher (typically by a factor of 60) than the speed of the synchronous digital circuitry. For a given speed of the synchronous circuitry the present circuit can achieve an input bandwidth several orders of magnitude larger than the scheme of E. Roza.